`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: SJTU
// Engineer: Yricky
// 
// Create Date: 2019/10/27 13:17:51
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
    input clk,
    input switch,
    output [13:0] a2g_data_add,
    output [7:0] a2g_add
    );
    
    wire clk_10ms;
    wire clk_100ms;
    wire clk_1s;
    wire clk_1ms;
    
    wire [3:0] displayCache;
    wire [6:0] a2g_data_cache;
    wire [7:0]a2g_select_array;
    reg [9:0]count;
    reg [47:0]num;
    reg [31:0]out_data_cache;

    reg [2:0]lr;

    always @(*)
    begin
    num='h518030910206;
    end
    
    always @(posedge clk_10ms)
    begin
    count <=count+1;
    if(count==100)
    begin
    count<=0;
    if(switch==1)
        lr<=lr+1;
    if(switch==0)
        lr<=lr-1;
    end
    case(lr)
    3'b000:
    begin
    out_data_cache<=num[31:0];
    end
    3'b001:
    begin
    out_data_cache<=num[35:4];
    end
    3'b010:
    begin
    out_data_cache<=num[39:8];
    end
    3'b011:
    begin
    out_data_cache<=num[43:12];
    end
    3'b100:
    begin
    out_data_cache<=num[47:16];
    end
    3'b101:
    begin
    out_data_cache<=num[31:0];
    end
    default:
    begin
    if(switch==1)
        lr<=0;
    if(switch==0)
        lr<=3'b100;
    
    end
    endcase 
    end
    
    
    
    
    Clock clock(.clk(clk),
                   .clk_1ms(clk_1ms),
                  .clk_10ms(clk_10ms),
                  .clk_100ms(clk_100ms),
                  .clk_1s(clk_1s));  
                     
                  
    OctaSelect selector(.select_clk(clk_1ms),
                          .data_in(out_data_cache),
                          .data_out(displayCache),
                          .digit_sel(a2g_select_array)); 
                          
                          
    SevenSegEncoder encoder(.D(displayCache),
                .A_2_G(a2g_data_cache));
                
    Display display(.a_2_g_in(a2g_data_cache),
                         .a_2_g_out(a2g_data_add),
                         .digital_sel_in(a2g_select_array),
                         .digital_sel_out(a2g_add));
                         
                  
endmodule
